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Theoretically, the judicial branch, via defamation law.

> There's some realistic stuff here, like exporting a Powerpoint presentation to PDF, but it seems likely that these examples were chosen from many more that favoured the M1. Which…

It looks like sysctl shows the cache info for the little cores, at least by default: hw.cachelinesize: 128 hw.l1icachesize: 131072 hw.l1dcachesize: 65536 The reported L1I and L1D m…

A quick search suggests ARM's own designs tend to use 64-byte cache lines, but perhaps this is something the SoC vendors can customize? AFAIK, Qualcomm's recent parts use ARM-desig…

Interestingly, the M1 (and probably other Apple Silicon CPUs) is an exception: % sysctl hw.cachelinesize hw.cachelinesize: 128